# Demo Subtitles — CodeVista + METIS: Verilog UART Controller

## Step 1 — Show design documents in METIS

- The design documents — the "ground truth" for implementation
- AI agents cannot know these requirements without access to a Knowledge Base
- Metis can process multiple types of format: pdf, docx, xlsx, pptx, md,...
- Handles complex content — tables, merged cells, images, diagrams, color-coded structures
- Scales to thousands of files — one unified, searchable knowledge base

## Step 2 — Upload to METIS

- Upload once — CodeVista can query anytime via MCP
- METIS automatically parses, chunks, and creates semantic index
- Content is indexed — not just stored. Every chunk is searchable by meaning, not just keywords
- AI-generated tags with confidence levels — human reviewers approve or reject

## Step 3 — CodeVista queries METIS + generates Verilog

- CodeVista accesses the knowledge base via MCP — right inside the IDE
- Developers never leave their familiar workspace — the specs come to them
- Every specification retrieved is traceable to a source document — with citations
- These values come from YOUR documents — not from AI training data
- No hallucination — if the knowledge base doesn't have it, METIS says so

## Step 4 — Run simulation

- 17 tests — baud rate, TX, RX, loopback — all PASS
- The code doesn't just compile — it functionally matches the protocol specification
- From specification documents to verified working design — in one session

## Step 5 — Show waveform

- The waveform is the "visual proof" — equivalent to a working UI for software
- Start bit → 8 data bits → Even parity → Stop bit — exactly as specified
- TX sends, RX receives — every byte matches

## Closing

- METIS: the central context engine that gives AI tools your actual specifications
- On-premise — your designs never leave your network
- One knowledge base, multiple AI consumers — coding, testing, documentation
- Works for any HDL: Verilog, VHDL, SystemVerilog