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{"sheet":"UART Signals","index":0,"n_rows":12,"n_cols":6,"rows_kept":12,"cut":false,"hidden":false,"merged":[]}
["Signal","Direction","Width (bits)","Description","Active Level","Notes"]
["clk","input",1,"System clock","Rising edge","50 MHz"]
["reset","input",1,"Synchronous reset","Active HIGH","Resets all FSMs"]
["tx_data[7:0]","input",8,"Parallel transmit data","-","Latched on tx_start"]
["tx_start","input",1,"Start TX transmission","Active HIGH","Single-cycle pulse"]
["tx","output",1,"Serial transmit line","-","Idle HIGH, start bit LOW"]
["tx_done","output",1,"TX complete indicator","Active HIGH","Single-cycle pulse"]
["tx_active","output",1,"TX in progress","Active HIGH","HIGH during transmission"]
["rx","input",1,"Serial receive line","-","Directly from external source"]
["rx_data[7:0]","output",8,"Received parallel data","-","Valid when rx_ready=1"]
["rx_ready","output",1,"RX data ready","Active HIGH","Single-cycle pulse"]
["parity_error","output",1,"Parity check failed","Active HIGH","Valid with rx_ready"]

{"sheet":"Parameters","index":1,"n_rows":10,"n_cols":2,"rows_kept":10,"cut":false,"hidden":false,"merged":[]}
["Parameter","Value"]
["Baud Rate","9600 bps"]
["Data Bits","8"]
["Parity","Even"]
["Stop Bits","1"]
["Frame Format","8E1"]
["System Clock","50 MHz"]
["16x Divider","326"]
["Bit Period","104.167 us"]
["Frame Duration","1.146 ms (11 bits)"]